VHDL编程之可逆计数器

Crane posted @ 2009年6月18日 13:58 in Programing with tags 编程 VHDL , 14090 阅读

数字逻辑学了一个学期，始终都是一堆的门元件和触发器接来接去，实在是搞得人有点晕乎，到了最后大规模集成电路的时候，终于不用（好像也不可能）那些方法了，话说coding the world不是没有道理的，这大规模的电路设计最后还是得软件来搞，可惜还没到CPLD/FPGA的地步，我们就搞了一个用VHDL做的4位（其实用VHDL 的话这个位数只是个数字而已）可逆计数器，觉得蛮有意思，代码丢在这里，万一以后想到查呢？

题目是这样的：

设计一个能清0，置数和进位输出的增1/减1的4位二进制计数器。

输入信号clr为清0端，低电平有效，信号ld为置数端，也是低电平有效，将A，B，C，D的输入值送到计数器中，并立即在Qa，Qb，Qc，Qd中输出。输入信号m为模式选择端，m＝1时为加1计数，m＝0时为减1计数。当cp端输入一个上升沿信号时进行一次计数，有进位/借位时qcc输出一个负脉冲。

代码如下

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity counte is
port(cp,clr,ld,m:in std_logic;
abcd:in std_logic_vector(3 downto 0);
qcc:out std_logic;
qcount:out std_logic_vector(3 downto 0));
end;
architecture count of counte is
begin
process(cp,clr,ld)
begin
if(clr='0')then
qcount<="0000";
if(m='0')then
qcc<='0';
end if;
elsif(ld='0')then
if(abcd="0000" and m='0')then
qcount<=abcd;
qcc<='0';
elsif(abcd="1111" and m='1')then
qcount<=abcd;
qcc<='0';
else
qcount<=abcd;
qcc<='1';
end if;
elsif(cp'event and cp='1')then
if(qcount="1110" and m='1')then
qcount<="1111";
qcc<='0';
elsif(m='1')then
qcount<=qcount+1;
qcc<='1';
end if;
if(qcount="0001" and m='0')then
qcount<="0000";
qcc<='0';
elsif(m='0')then
qcount<=qcount-1;
qcc<='1';
end if;

end if;
end process;
end count;

其中字母基本上和上面要求对应，就是上边的qcount对应Qa，Qb，Qc，Qd。

感觉这样的begin和end的配对，而且整个程序看起来和PASCAL还是有点像的。

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